Provides control functions to the MAC; 2KB RX Data FIFO and 256B TX Data FIFO; Separate RX and TX DMA Controllers; Internal storage for 64 TX Buffer. Apr 7, 2008 - Receive Buffer Descriptors. Transmit MAC Status Register (Offset: 0x460). Pre-DMA Command Exchange Register for TCP Segmentation (Offset: 0xCF4)....228. Send Data Completion Control Registers. For high throughput the MAC driver must make efficient use of the DMA and avoid. The buffer to transmit is described by the descriptor passed into the function.
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